Intel Stratix 10 TX Device part #1ST280EU1F50E2LG | DEX
Intel 1ST280EU FPGA - Field Programmable Gate Array part # 1ST280EU1F50E2LG chips & semiconductors Intel

Intel Stratix 10 TX Device part #1ST280EU1F50E2LG

Regular price
$71,040.00
Sale price
$71,040.00
Regular price
$71,040.00
Sold out
Unit price
per 
Shipping calculated at checkout.

Intel Stratix 10 DX devices are based on a monolithic core fabric featuring the new Intel Hyperflex core architecture. The Intel Hyperflex core architecture delivers higher performance and up to 70% lower power compared to previous generation high-end FPGAs. Along with this performance breakthrough, the Intel Hyperflex core architecture delivers a number of advantages including:

 Higher Throughput—Capitalizes on high core clock frequency performance to obtain throughput breakthroughs

 Improved Power Efficiency—Uses reduced IP size, enabled by Intel Hyperflex, to consolidate designs which previously spanned multiple devices into a single device, thereby reducing power by up to 70% versus previous generation devices

 Greater Design Functionality—Uses faster clock frequency to reduce bus widths and reduce IP size, freeing up additional FPGA resources to add greater functionality

 Increased Designer Productivity—Boosts performance with less routing congestion and fewer design iterations using Hyper-Aware design tools, obtaining greater timing margin for more rapid timing closure

In addition to the traditional user registers found in the Adaptive Logic Modules (ALM), the Intel Hyperflex core architecture introduces additional bypassable registers everywhere throughout the fabric of the FPGA. These additional registers, called Hyper-Registers are available on every interconnect routing segment and at the inputs of all functional blocks.

The Hyper-Registers enable the following key design techniques to achieve the 2X core performance increases:

• Fine grain Hyper-Retiming to eliminate critical paths

• Zero latency Hyper-Pipelining to eliminate routing delays

• Flexible Hyper-Optimization for best-in-class performance

By implementing these techniques in your design, the Hyper-Aware design tools automatically make use of the Hyper-Registers to achieve maximum core clock frequency.

 

Intel Stratix 10 TX Device part #1ST280EU1F50E2LG

ITL:1ST280EU1F50E2LG