Intel Central Processing Unit part #: CM8063501293200S R1A0 | CPU | DEX

Intel Central Processing Unit part #: CM8063501293200S R1A0 Processor Feature Details:

• Up to 8 execution cores • Each core supports two threads (Intel® Hyper-Threading Technology), up to 16 threads per socket • 46-bit physical addressing and 48-bit virtual addressing • 1 GB large page support for server applications • A 32-KB instruction and 32-KB data first-level cache (L1) for each core • A 256-KB shared instruction/data mid-level (L2) cache for each core • Up to 20 MB last level cache (LLC): up to 2.5 MB per core instruction/data last level cache (LLC), shared among all cores • The Intel® Xeon® processor E5-4600 product family supports Directory Mode, Route Through, and Node IDs to reduce unnecessary Intel QuickPath Interconnect traffic by tracking cache lines present in remote sockets. 

System Memory Support

• Intel® Xeon® processor E5-1600/E5-2600/E5-4600 product families supports 4 DDR3 channels • Unbuffered DDR3 and registered DDR3 DIMMs • LR DIMM (Load Reduced DIMM) for buffered memory solutions demanding higher capacity memory subsystems • Independent channel mode or lockstep mode • Data burst length of eight cycles for all memory organization modes • Memory DDR3 data transfer rates of 800, 1066, 1333, and 1600 MT/s • 64-bit wide channels plus 8-bits of ECC support for each channel • DDR3 standard I/O Voltage of 1.5 V and DDR3 Low Voltage of 1.35 V • 1-Gb, 2-Gb and 4-Gb DDR3 DRAM technologies supported for these devices: — UDIMMs x8, x16 — RDIMMs x4, x8 — LRDIMM x4, x8 (2-Gb and 4-Gb only) • Up to 8 ranks supported per memory channel, 1, 2 or 4 ranks per DIMM • Open with adaptive idle page close timer or closed page policy • Per channel memory test and initialization engine can initialize DRAM to all logical zeros with valid ECC (with or without data scrambler) or a predefined test pattern • Isochronous access support for Quality of Service (QoS), native 1 and 2 socket platforms - Intel® Xeon® processor E5-1600 and E5-2600 product families only • Minimum memory configuration: independent channel support with 1 DIMM populated • Integrated dual SMBus master controllers • Command launch modes of 1n/2n • RAS Support (including and not limited to): — Rank Level Sparing and Device Tagging — Demand and Patrol Scrubbing — DRAM Single Device Data Correction (SDDC) for any single x4 or x8 DRAM device failure. Independent channel mode supports x4 SDDC. x8 SDDC requires lockstep mode — Lockstep mode where channels 0 & 1 and channels 2 & 3 are operated in lockstep mode — The combination of memory channel pair lockstep and memory mirroring is not supported — Data scrambling with address to ease detection of write errors to an incorrect address. — Error reporting via Machine Check Architecture — Read Retry during CRC error handling checks by iMC — Channel mirroring within a socket Channel Mirroring mode is supported on memory channels 0 & 1 and channels 2 & 3 — Corrupt Data Containment — MCA Recovery • Improved Thermal Throttling with dynamic Closed Loop Thermal Throttling (CLTT) • Memory thermal monitoring support for DIMM temperature via two memory signals, MEM_HOT_C{01/23}_N

ITL:CM8063501293200S R1A0

CM8063501293200S R1A0