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Xilinx Field Programmable Gate Array - FPGA - part # XCKU060-2FFVA1156E

Xilinx Field Programmable Gate Array - FPGA - part # XCKU060-2FFVA1156E

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Xilinx® UltraScale™ architecture comprises high-performance FPGA, MPSoC, and RFSoC families that address a vast spectrum of
system requirements with a focus on lowering total power consumption through numerous innovative technological

RF Data Converter Subsystem Overview

Most Zynq UltraScale+ RFSoCs include an RF data converter subsystem, which contains multiple radio
frequency analog to digital converters (RF-ADCs) and multiple radio frequency digital to analog
converters (RF-DACs). The high-precision, high-speed, power efficient RF-ADCs and RF-DACs can be
individually configured for real data or in most cases can be configured in pairs for real and imaginary I/Q
data. See RF-ADCs and RF-DACs sections.

Soft Decision Forward Error Correction (SD-FEC) Overview

Some Zynq UltraScale+ RFSoCs include highly flexible soft decision FEC blocks for decoding and encoding
data as a means to control errors in data transmission over unreliable or noisy communication channels.
The SD-FEC blocks support low-density parity check (LDPC) decode/encode and Turbo decode for use in
5G wireless, backhaul, DOCSIS, and LTE applications.

Processing System Overview

Zynq UltraScale+ MPSoCs and RFSoCs feature dual and quad core variants of the Arm Cortex-A53 (APU)
with dual-core Arm Cortex-R5F (RPU) processing system (PS). Some devices also include a dedicated Arm
Mali™-400 MP2 graphics processing unit (GPU)




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